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HPE plans an ambitious reengineering of its server architecture

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November 24, 2016

We learned today that HPE is currently planning one of the most determined and ambitious reengineering of its server architecture. The company says it's huge and will be felt for several years.

Here's what we know so far-- dubbed 'The Machine' it's being touted as being a memory-driven server in which a universal pool of non-volatile memory is accessed by large numbers of specialized cores, and in which data is not moved from processor to processor, but in which data can stay still while different processors are brought to bear on either all of it or subsets of it.

Some of the goals include not moving masses of data to servers across relatively slow interconnects, and gaining the highest processing speeds of in-memory computing without using expensive DRAM.

The main benefit is hoped to be a quantum leap in compute performance and energy efficiency, providing the ability to greatly extend computation into new workloads as well as speed analytics, HPC and other existing workloads.

It involves various developments at virtually every level of server construction, from every chip design, through system-on-chips, silicon photonics chips and message protocols, server boards, CPU-memory access and architectures, chassis, network fabrics, operating system code and application stacks from which input/output may be completely redesigned.

This is major. There is also a real chance that HPE may have over-reached itself and that, even if it does deliver The Machine to the market, hidebound users and suspicious developers may not adopt it.

It appears that 'The Machine' is an extraordinary high-stakes bet by HPE, so let's try and assess the system.

The planned new servers are basically a bunch of processors accessing a universal memory pool via a phonics interconnect.

We can envisage five technology attributes of The Machine:

  • Heterogeneous specialised core processors or nodes
  • Photonics-based CPU to universal memory pool interconnect
  • Universal non-volatile memory pool
  • Software programming scheme
  • The cores
  • The cores are processor cores focussed on specific workloads, meaning not necessarily x86 cores. They could also be ATOMs, ARMs or something else or a mix, but probably single socket and multi-core.

    A processor in The Machine is instantiated on a SOC (System On a Chip) along with some memory and photonic interconnect. The SOC, which is a computational unit, could link to 8 DRAMs in a mocked-up system. The interconnect then goes to a fabric switch and then on to shared memory.

    Note: a SOC on one node talks via the fabric (through bridges or switches) to persistent memory on the other nodes without involving the destination node’s SOC.

    Photonics is an integration of silicon and lasers to use light signals in a networking fabric that is faster than pumping electrons down a wire.

    The Machine’s SOCs run a stripped-down Linux and interconnect to a massive pool of universal memory through the photonics fabric.

    This memory is intended to use HPE’s Memristor technology, which is hoped to provide persistent storage, memory and high-speed cache functions in a single, cost-effective device.

    When HPE talks of a massive pool, it has hundreds of petabytes in mind, and this memory is both fast and persistent.

    However, we should not think of The Machine's processors accessing memory in the same manner that a current server's x86 processor accesses its directly connected DRAM via intermediate on-chip caches, with the DRAM being volatile and having its contents fetched from mass storage.

    The Machine's memory was originally going to be made from Memristor technology, which would replace a current server’s on-chip caches and DRAM, but the delayed timescale for that meant a stop-gap scheme involving DRAM and Phase-Change Memory appeared in April 2015.

    HP’s CTO Marin Fink, the senior redesign engineer of The Machine, said the new systems would be delivered in a three-phase project.

    Phase 1 is a working prototype, with phase 2 an actual but intermediate system, and phase 3 the full Memristor-based system.

    SanDisk (now Western Digital) became part of HPE’s memory-driven computing ideas in October 2015. We can imagine that its ReRAM replaced the Phase Change Memory notion in the phase 2 Machine.

    The phase 2 machine has server nodes (CPU + DRAM + optical Interconnect) sharing a central pool of slower-than-DRAM non-volatile memory, with potentially thousands of these server nodes (SOCs). HPE’s existing Apollo chassis could be used for it.

    Phase 3 would then have a Memristor shared central pool. If the server nodes retain their local DRAM then HPE will have failed in its attempt to collapse the memory hierarchy to just a Memristor pool.

    But 'The Machine' has been delayed by a few months, and that's expected by such a major redesign. For instance, Fink told the HP Discover 2015 audience at Las Vegas that “a working prototype of The Machine would be ready in time for next year's event.”

    Bits of one have been seen so far, but at the time of the 2015 Discover event Fink posted a blog, ”Accelerating The Machine” which was actually about The Machine’s schedule delay. We'll keep you posted as we learn more about this significant reengineering project.

    Source: HPE.


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