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Gen-Z: a new scalable, high-performance bus linking computers and memory

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October 11, 2016

A group of server hardware suppliers have got together as a newly formed group to develop Generation Z-- a new scalable, high-performance bus architecture seamlessly linking computers, servers and memory in one fell swoop.

Dubbed the 'Gen-Z Consortium, it consists of an open, non-proprietary transparent industry standards body. The Gen-Z founders believe that open standards provide a new level playing field to promote easier adoption, innovation and choice for IT enterprise customers.

The consortium members are (in alphabetical order) AMD, ARM, Broadcom, Cavium, Cray, Dell-EMC, Hewlett Packard Enterprise (HPE), Huawei, IBM, Lenovo, Mellanox Technologies, Micron, Microsemi, Red Hat, Samsung, Seagate, SK Hynix, Western Digital and Xilinx. It's an impressive list of vendors in deed.

To be sure, a 'memory semantic fabric' (MSF) handles all data communication as memory operations, such as load/store, put/get and atomic operations typically used by a processor or group of processors.

Memory semantics are optimal at sub-microsecond latencies from CPU load command to register and store in most modern applications. This is unlike storage accesses which are block-based and managed by complex, code intensive, software stacks.

The consortium's announcement release states-- "The emergence of low latency, storage-class memory, and the overall demand for rack scale resource pools require a new approach to data access."

Its 'background thinking' is that memory tiers will become increasingly important, and rack-scale composability requires a high bandwidth, low latency fabric which must seamlessly plug into existing ecosystems without requiring OS changes in any way.

The project looks to be quite a challenge. It provides four standard Gen-Z interconnect characteristics:

  • High bandwidth and low latency through a simplified interface based on memory semantics, scalable from tens to several hundred GB/sec of bandwidth, with sub-100 nanosecs load-to-use memory latency.
  • It supports scalable memory pools and resources for real-time analytics and in-memory applications
  • Gen-Z is said to be highly software compatible with no required changes to the operating system
  • Gen-Z scales from simple, low cost connectivity to highly capable, rack scale interconnect applications.
  • The core specification, covering the architecture and protocol, will be finalized sometime in late November of this year, and the Gen-Z Consortium is accepting new members.

    It will be interesting to see if and when the IT industry adopts the new standard and what kind of timeframe we might be looking at if does get adopted by the major users.

    Source: Cisco.


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