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Western Digital starts its test production of 64-layer 3D NAND

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July 27, 2016

Via its recently acquired company SanDisk, Western Digital (WDC) and Toshiba have started a production test of 64-layer 3D NAND technology.

These 3rd generation Bi-CS3 chips are being made at Yokkaichi's Japanese facilities, operated in a joint venture between Western Digital and Toshiba.

Currently, Samsung is shipping its 48-layer 3D V-NAND chips to the industry. To be sure, 64 layers is the next step to increase per-chip capacity further, we are told.

Dr Siva Sivaram, vice president for memory technology at Western Digital made a statement-- ``BiCS3 will feature the utilization of 3-bits-per-cell technology along with various advances in high aspect ratio semiconductor processing.``

``The first chips will have 256 Gbit capacities but this will grow to 500Gbits,`` he added.

For their part, BiCS2 48-layer chips have 256 Gbit capacities so there is no advantage until higher-capacity chips are produced.

This would suggest that the 64-layer chips have had a die reduction compared to the 48-layer BiCS2 chips, and that WDC and Toshiba are proving that the technology and its production process before embarking on making higher capacity chips.

Initial BiCS3 product output will start later this year with meaningful commercial volumes starting in the first half of next year.

OEM sampling of BiCS3 chips will start this quarter, with volume shipping of the chips for the retail market in the fourth quarter of this year.

Most likely, we can expect Samsung 64-layer V-NAND chips to be available in 2017 as well. Both Intel and Micron are also on a 3D journey with NAND and, more excitingly, faster XPoint.

Source: Western Digital.

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