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StoreServ arrays now utilize an ASIC in their storage solutions

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July 4, 2016

StoreServ arrays now utilize an ASIC in their storage solutions to accelerate various operations, and this is redesigned for each major generation of the system.

The current design is generation 5. Siamak Nazari is an HPE fellow and StoreServ system architect, and is heavily involved in the design of the forthcoming generation 6 ASIC family of processors.

An ASIC design has to last for at least five years once systems using it start shipping, which means Nazari has to peer into the future and discern what the characteristics of storage array media, storage array software and accessing host requirements will be between 2018, when gen 6 ASIC use is expected to start, and 2023 or thereabouts.

He works with the hardware team in designing the ASIC chip. In HPE's storage business organization terms, he is part of the system-defined storage operation, headed up by Vish Mulchand, who reports to HPE's storage vice president, Manish Goel.

The generation 5 ASIC has been active during a general array evolution from pure disk and hybrid flash/disk use to all-flash designs, with consequent dramatic reduction in media access latency.

Nazari assumes that there will be an evolution to post-NAND media, such as Resistive RAM (ReRAM), with Memristor being in that general category, 3D XPoint and maybe STT-RAM (Spin Transfer Torque RAM) and PCM (Phase Change Memory).

The ASIC should cover the general attributes exposed by these device technologies, such as lower latency. Nazari said that HPE sees a role for XPoint as well as ReRAM. He said the HPE-SanDisk (now WDC) partnership was ongoing, and driven by HPE's server operation.

So Nazari is seeing HPE servers and others using ReRAM and XPoint media with their sub-microsecond access latency when used in DIMM form.

He is also expecting NVMe over Fabrics style networking with much lower network latency, which puts more demands on the array to respond commensurately faster than with other solutions.

He also sees the StoreServ array segment having up to six general components; accessing server hosts, host-array fabric, array controller complex with the ASIC, controller-media fabric, and the array’s media drives.

He says the array controller-media fabric is Fibre Channel and SAS with a transition to NVMe fabric over the nest two to three years. Nazari is free to innovate in the ASIC area.

He adds that it has built-in storage semantics and assumes a single system domain. An XPoint SSD will have roughly 10 microsecs latency, which compares to NVMe NAND’s 60 to 100 microseconds.

SAS will add about 10 to 20 microseconds to that, and has well-defined error-handling protocols, lacking in NVMe.

Source: HPE.

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