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Intel unveils its Xeon E7-8800 and E7-4800 v4 CPU family

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June 6, 2016

Following the recent announcement of its Xeon E5 v4 server chips, Intel has unveiled its new family of Xeon E7-8800 and E7-4800 v4 CPUs.

However, while the E5 v4 processors are mostly designed for scale-out systems, the E7 v4 series announced today is aimed mostly at scale-up work.

To be sure, complex analytics and in-memory database jobs that need lots of memory per node will find their home with the new processors.

An eight-socket E7 v4 system can support up to 24 TB of RAM, twice that of the previous generation that launched in mid-2015.

The E7 v4 family uses the Broadwell microarchitecture, and are fabricated using a 14 nm process. Additionally, they can be dropped right into sockets for E7 v3s, easing any upgrades.

Intel says you'll get about up to a 1.3 times performance boost by switching from v3 to v4.

But if that upgrade seems too sudden, Intel might have another issue-- it says one-hundred 10-core four-socket E7-4870 v1 chips can be replaced with thirty-three 24-core four-socket E7-8890 v4 CPUs.

Alternatively, 20 two-socket 22-core E5-2699 v4 CPUs deliver the same transactional performance as nine four-socket 24-core E7-8890 v4 components.

Fewer cores means fewer dollars spent on enterprise software licenses. The E7 v4 chips feature all sorts of architectural features that are present in the E5 v4 cousins.

Those include software interrupts delivered directly into virtual machines; reduced overhead when the processor enters and leaves a VM; faster cryptographic operations; tighter controls to prevent obscure code running in kernel mode from accessing userspace; cache usage tracking; and a few more features.

The new processors feature up to 24 cores per socket and up to 60 MB of last-level cache, up from the previous generation's 18 cores and 45 MB.

There's also Broadwell's cluster-on-die technology that chops up each chip into a two-socket NUMA box, allowing the operating system to carve the processor into two NUMA domains.

One domain stays on one ring of cores while the other domain is on the second ring. Overall, the ring structure is described by Intel's documentation.

Source: Intel.

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