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ARM launches its new 32-bit Cortex-M7 processor

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September 24, 2014

Earlier today, ARM has revealed its new 32-bit Cortex-M7 processor, which will sit at the top of its microcontroller-grade family of cores in terms of performance.

ARM's previous top-of-the-line processor was the Cortex-M4. The M7 has twice the DSP power of the M4 by executing twice as many instructions simultaneously, and it also helps that the M7 can operate at a higher clock frequency than the M4.

"The Cortex M7 has a superscalar pipeline which can execute two instructions simultaneously," an ARM source told us today.

"The Cortex-M4 can execute just one instruction at a time. This is where most of the speed-up comes from. The Cortex-M7 can run at a higher clock frequency than the Cortex M4.

Together these give on average two-times uplift in DSP performance for Cortex-M7 over the Cortex-M4."

DSP (digital signal processing) is particularly useful for efficiently juggling incoming streams of audio and video data, and performing fast motor control-– better than a generic CPU core can manage.

By doubling the performance, ARM says that appliances and gadgets using the M7 can more quickly perform the complex math required to finely control motor movement in robots, analyze microphone, touchscreen, and other sensor data, and then encrypt the telemetry before it's sent over the air.

That means ovens with better voice-recognition software when you speak to them, drones with tighter flight control, tiny sensor networks in walls sensing humidity earlier, and so on.

To be sure, all of this depends on the system-on-chips the M7 cores end up in, and the software running on them.

Manufacturers can set the clock speed, and enable and disable various features as they desire. Hardware and software engineers may have other ideas for products and bottlenecks in mind to stuff up ARM's dream of pumping more intelligence into our every day lives.

More intelligent SoCs means less data flying back to base, since the microcontrollers can make more of their own decisions, which will result in simpler networks and less information to intercept, but it'll also make the code on the cores more complex, and that means more bugs.

The M7 has a six-stage superscalar pipeline, with branch prediction, compared to the M4's three-stage, and runs the usual 32-bit ARMv7 instruction set.

It's backed by the Keli CMSIS DSP library, and includes a single and double precision FPU. At least the DSP functionality is within the instruction set, albeit as an extension, rather than discrete DSP silicon.

The M7 aims for realtime determinism with tightly coupled memories and a 12-cycle interrupt latency. You can also use two M7 cores in lock step running the same code – one following two cycles behind the other – so that potential glitches can be detected by external electronics if the two CPUs suddenly behave slightly differently.

Atmel, Freescale and ST Micro Electronics have already snapped up licenses to pump out chips with M7 cores in the 90 nanometer to 40 nm process range. Each core taking up a 0.1mm square of silicon, before the manufacturer whacks peripherals, the control logic and the power management into a chip package.

Source: ARM Inc.

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