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IBM produces new hybrid PCM/NAND server flash card

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May 8, 2014

IBM has released a new Phase Change Memory product research and demo effort-- a hybrid PCM/NAND server flash card that has at least twelve times lower latency than an enterprise PCIe flash card.

The hybrid card completed 99.9 percent of write requests within 240 microseconds, equal to 1 millionth of a second. A consumer-class SSD took 275 times longer before it started writing the data in the test IBM used.

Phase Change Memory (PCM) uses a chemical state change (from amorphous to crystalline) in a chalcogenide alloy, with the differing resistance levels of the two states signalling a binary 1 or 0.

The change in state is caused by controlled heating. PCM has been trumpeted as a follow-on technology to NAND, which is running out of acceptable error rates and endurance as cell geometry shrinks below 16 nm.

PCM cells can be written or reprogrammed to at least 106 times. The performance and price characteristics of PCM lie between DRAM and NAND.

But overall, producing PCM has been problematic at the best of times, partly because it has a relatively high write latency, and so this IBM Research demonstration is significant.

Ioannis Koltsidas, a semiconductor memory boffin at IBM's Zurich labs, in conjunction with colleagues there and at the University of Patras, built a hybrid PCIe card furnished with both NAND and PCM and tested its performance.

They called it a Prototype Storage Subsystem (PSS). Micron P5Q 128 Mbit PCM chips were used with 90nm technology nodes. These were commercially available when the project started at the end of 2012.

The write time for a sector I/O (512B + 64B) was 1.15 msecs with the read time being 75.24 µsecs so it's a tad asymmetrical.

More sub-banks on the card make for a better write performance while more sub-channels improve the read performance.

Koltsidas states-- "We chose a configuration that minimises write latency without severely penalising reads." He adds-- "The design of PSS targets storage workloads that are dominated by small (eg, 4 KB) random I/O operations and aims to achieve low, predictable latency with reads and writes."

The testing results included a chart of latency profiles for the PSS card, an MLC flash PCIe card, and a TLC (3-layer cell) SSD - the baseline in effect.

The test used "per-I/O latency measurements for two hours of uniformly random 4KB writes at QD=1, after 12 hours of preconditioning with the same workload."

The PSS card's latency was 12 times lower than an MLC SSD but this is not such a big deal, not relatively. If we want faster flash we could use an SLC flash PCIe card. However it used old PCM chips, 18 months old technology, and newer PCM chips may well be better.

With this result Koltsidas said that PCM is a promising new technology and suggests the following use cases for a PCM card:

  • Caching device
  • Metadata store
  • Backend for low-latency key-value store
  • Tiered storage device in a hybrid configuration with Flash
  • That seems sensible, but of course, whether IBM will build such a card is another question. We think it's unlikely to leave the lab.

    Perhaps Micron or another PCIe flash card supplier might make one though, if the cost profile is acceptable and customers will pay sufficient money for the performance improvement.

    In other IT news

    At a cost of one billion dollars, HP has finally unveiled its two-year campaign promoting its open-source cloud, now rebranded as Helion. The company says it will be spending on R&D, the development of cloud products and hiring “hundreds” of experts in a new OpenStack professional services practice.

    Various experts are being hired to cover planning advice, building and migration, and operations and management.

    Underpinning this will be a tried and tested HP-branded version of the OpenStack distro released in two packages - one free, the other commercial.

    The Helion OpenStack Community edition is the free version but will feature relatively limited functionality, for use in pilot programs and testing.

    The commercial edition of the HP-branded code is promised for sometime in June, and that will have been tested to scale to thousands of servers. It will support third-party plug-ins, come with management tools, and run with a choice of hypervisors and hardware.

    According to Hewlett-Packard, Helion OpenStack follows the core of the OpenStack trunk.

    A development platform that’s based on Cloud Foundry will also be announced. Called the HP Helion Development Platform-as-a-service (PaaS), HP’s development service is due for a preview release in the third quarter of the year.

    Additionally, HP is offering Helion a financial umbrella should patent sharks come knocking at the door.

    HP will promise indemnification against IP infringement claims to direct customers and customers of service providers and resellers on Helion.

    The technology and legal push are to pave the way for a rollout of Helion OpenStack-based cloud services in 20 of HP’s 80 data centres in the next 1 1/2 year.

    Also, HP’s OpenStack will be “tightly integrated” with its server, storage and networking platforms including its 3Par, StorVirtual VSA and SDN Controller.

    Until now, HP had been building OpenStack code into only certain products, such as certain ARM-based servers in its Moonshot range.

    In the near future, HP says that ordinary ProLiant servers will ship with Helion OpenStack software and when you boot up they’ll search for their nearest Helion cloud.

    Bill Hilf, HP's vice president of converged cloud products and services, says his company is making a bold bet with the $1 billion OpenStack investment.

    “It’s a huge part or our strategic initiative for Hewlett Packard and a big part of HP’s turnaround, frankly,” he added.

    “Overall, so many vendors put these big numbers out there as we were prepared for this, we wanted to be clear this is not some fictional thing.”

    On indemnification, he said enterprise customers want a “large and trusted” brand standing behind OpenStack should they be attacked by a patent troll, which happens almost everyday in the industry nowadays.

    “It’s all about giving enterprise customers the confidence that if something were to happen, they are protected,” he said. “It’s all about confidence and the assurance that there is a vendor behind them.”

    In other IT news

    AMD said earlier today that it will create pin-compatible 64-bit x86 and ARM SoCs in a new initiative that it's calling Project SkyBridge.

    Overall, AMD has licensed the ARMv8 architecture and will design its own home-grown ARM-based processors.

    "AMD is the only company that can bridge ARM and the x86 ecosystems," said AMD's general manager of global business units Lisa Su at the announcement event in San Francisco yesterday.

    "We said we were going to be ambidextrous," said AMD CEO Rory Read, also at the event. "We were going to do something that no one else on earth could do."

    Pin compatibility, Su said, will bring "tremendous flexibility to the market," seeing as how an OEM can design and build a single motherboard that can be fitted with either an x86 or ARM SoC.

    "It really is a design framework," she said. "It's a family of products that we'll be putting out starting first in 20-nanometer technology." The first products in that family, planned for next year, will be what AMD has dubbed APUs – accelerated processing units – and will include AMD's Graphics Core Next (GCN) GPU technology.

    Both the ARM and x86 parts will be built around a heterogeneous system architecture HSA. AMD currently supports HSA in its "Kaveri" desktop and notebook chip, and its "Berlin" Opteron server chip, demoed at the Red Hat Summit in April.

    On the x86 side of the Project SkyBridge ambidexterity, the APUs will be based on a next-generation "Puma+" compute cores, an update to the "Puma" cores announced last week in the rollout of the low-power, low-cost "Beema" and "Mullins" SoCs.

    On the ARM side, Su said, "We're going to optimize 64-bit ARM Cortex A57, again in the same footprint as we have our x86 capability." These low-power ARM-based APUs will also be AMD's first HSA-capable chips that support Android.

    The first Project SkyBridge APUs will be targeted at the embedded and client markets. "It's an opportunity for us to help customers innovate, differentiate, and also reduce their time to market," Su said.

    For some markets (she used networking as an example) Project SkyBridge will allow customers to simplify their code base from one that now also includes MIPS and PowerPC devices, to just x86 and ARM running on a single motherboard design.

    Source: IBM.

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